1. Technical Field
The present invention relates to a voltage control circuit, and in particular to a voltage control circuit for controlling a power supply voltage applied to a level conversion circuit and a semiconductor device having such voltage control circuit.
2. Related Art
Recent semiconductor devices are required to operate at higher speeds with a lower power supply voltage. In order to meet this requirement, a boost voltage is generated within a semiconductor device by boosting an externally applied power supply voltage, so that the power supply voltage and the boost voltage are selectively used as necessary. A level conversion circuit is used in the semiconductor device in order to enable the combination use of the power supply voltage and the boost voltage. The boost voltage is used, for example, in a word line drive circuit in a semiconductor storage device, a block selection circuit in a memory cell, and a transfer gate activation signal generating circuit. The boost voltage is mainly used as a gate signal of a transistor forming the transfer gate.
When the power supply voltage is used as a gate signal in the transfer gate, the level of the transmitted signal becomes lower than the power supply voltage by a threshold voltage of the transistor. Such decrease in the signal level will induce deterioration in the operation speed and the operation region of the semiconductor device. Therefore, the boost voltage is used for preventing the decrease in the signal level.
For example, a method is used in which a boost voltage boosted higher than the value of the externally applied power supply voltage by the threshold voltage value of the transistor or more is generated internally, and applied to the gate signal. When such boost voltage that has been boosted higher than the power supply voltage value by the threshold voltage value of the transistor or more is used as a gate input, the level of the signal transmitted from the transfer gate can be held at the power supply voltage level. In this manner, the use of the boost voltage makes it possible to prevent the decrease of the signal level, and to prevent the deterioration in the operation speed and the operation range of the semiconductor device.
A case of a word line drive circuit in a semiconductor device will be described as an example of circuits using a boost voltage. The word line drive circuit has a function to output a plurality of boost voltages, being formed of a plurality of decoder circuits receiving an address signal, and a plurality of level conversion circuits for level-converting a decoder output to a boost voltage.
FIG. 1 shows configuration of a conventional word line drive circuit, and FIG. 2 illustrates operational waveforms of the word line drive circuit of FIG. 1.
FIG. 1 shows n sets of decoder circuits 10-1 to 10-n and level conversion circuits 11-1 to 11-n associated with the respective decoder circuits. The decoder circuits operate at an externally applied power supply voltage VEXT, while the level conversion circuits operate at a boost voltage VPP. Hereafter, when the decoder circuits 10-1 to 10-n and the level conversion circuits 11-1 to 11-n are represented with any of the subscripts 1 to n, the subscript denotes the number of the set to which they belong. The decoder circuits and the level conversion circuits will be represented as the decoder circuit 10 and the level conversion circuit 11 without any subscript when the set number need not be specified. The same applies to decoder outputs Dec-1 to Dec-n and conversion circuit output signals Out-1 to Out-n, and they shall be represented simply as Dec and Out when the set number need not be specified.
The decoder circuits 10 receive a decoder selection signal (an address signal in this case), and output a decoder output Dec. As shown in FIG. 2, the decoder output Dec is at a low level when the decoder circuits 10 are not in use. When in use, only the decoder circuit selected by a decoder selection signal outputs a high level (indicated by the solid line in FIG. 2), whereas the other non-selected decoder circuits output a low level (indicated by the broken line in FIG. 2). The high level here is a power supply voltage VEXT. The level conversion circuits 11 receive a decoder output Dec from the decoder circuits 10 and output a conversion circuit output signal Out. The signal level of the decoder output Dec is a power supply voltage VEXT/ground voltage GND, and the signal level of the conversion circuit output signal Out becomes a boost voltage VPP/ground voltage GND. This means that the signal level (high level) is level-converted from the power supply voltage VEXT to the boost voltage VPP in the level conversion circuit 11.
Describing the level conversion circuits 11, the level conversion circuit 11-1 for example is formed of load transistors Q1 and Q3 connected between a boost voltage line at the boost voltage VPP and a line at the ground voltage GND, drive transistors Q2 and Q4, and an inverter circuit INV1. The drain, source, and gate of the load transistor Q1 are connected to the drain of the drive transistor Q2, the boost voltage VPP, and the drain of the drive transistor Q4, respectively. The drain, source, and gate of the drive transistor Q2 are connected to the drain of the load transistor Q1, the ground voltage GND, and the decoder output Dec-1, respectively.
The drain, source, and gate of the load transistor Q3 are connected to the drain of the drive transistor Q4, the boost voltage VPP, and the drain of the drive transistor Q2. The drain, source, and gate of the drive transistor Q4 are connected to the drain of the load transistor Q3, the ground voltage GND, and the output of an inverter circuit INV1 for inverting the decoder output Dec-1. A conversion circuit output signal Out-1 is output from the node to which the gate of the load transistor Q1 and the drains of the load transistor Q3 and drive transistor Q4 are connected.
The remaining level conversion circuits also have the same configuration as described above.
In the circuit configuration described above, the decoder output Dec and the conversion circuit output signal Out are at a logic of the same phase, and their signal level (high level) is converted from the power supply voltage VEXT to the boost voltage VPP.
However, the level conversion circuits 11 described above have problems in that they are prone to generate through current in the transistors and to induce gate breakdown. These problems are attributable to the fact that the level conversion circuits 11 are directly connected to the boost voltage line at the boost voltage VPP and constantly applied with a high voltage. The level conversion circuits 11 output a boost high level only when the decoder output Dec from a decoder circuit 10 selected by an address is a high level. On the other hand, the level conversion circuits 11 receiving a decoder output from the decoder circuits 10 which are not in use or not selected output a low level. Accordingly, the level conversion circuits 11 are left in such a stand-by state (low level output state) for most of the operating time of semiconductor device. Even during the low level output state, the level conversion circuits 11 are applied with the boost voltage VPP which is not used effectively.
The proportion of the level conversion circuits placed in the stand-by state becomes higher as the memory capacity becomes greater. The increase of the memory capacity increases the quantity of decoder circuits 10 to be arranged. When 256 (n=256) decoder circuits 10-1 to 10-256 are arranged, for example, one of the 256 decoder circuit is selected and only one level conversion circuit outputs a high level, while the remaining 255 conversion circuits output a low level. Even if the memory capacity is quadrupled, only one of the level conversion circuits outputs a high level, while the remaining 1023 level conversion circuits output a low level. In this manner, the majority of the level conversion circuits output a low level in the stand-by state.
A description will be made of stress applied to the level conversion circuits 11 when the level conversion circuits 11 output a low level and of a breakdown mode.
The level conversion circuits 11 are applied with the boost voltage VPP. The boost voltage VPP is boosted in a pump circuit (boost voltage generating circuit) (not shown) using capacity coupling, and is the highest power supply voltage in the semiconductor device chip. As described before, the boost voltage is used in various circuits such as the word line drive circuit, a block selection circuit in a memory cell, and a transfer gate activation signal generating circuit. Being used by the various circuits, the boost voltage is charged and discharged most acutely and repeatedly.
Therefore, the boost voltage VPP is caused to generate a large ripple Rp (FIG. 1) by the pumping operation of the boost voltage generating circuit. When the level conversion circuit 11 outputs a low level, the gate of the load transistor Q1 is at the ground voltage GND, while the source and the drain are at the boost voltage VPP. Accordingly, the channel region of the load transistor Q1 is also at the boost voltage VPP, and the boost voltage VPP is applied to an entire gate oxide film. When the ripple Rp occurs in the boost voltage VPP, the stress becomes higher by the voltage of the ripple Rp. The ripple Rp will deteriorate the gate oxide film of the load transistor Q1, which may result in increase of the leak current and occurrence of short-circuit Sh (FIG. 1) in the gate oxide film. Further, when the ripple occurs while the logic of the level conversion circuit is being shifted, through current it (FIG. 1) may occur in the level conversion circuit, resulting in breakdown of the load transistor Q1.
Methods of applying a power supply voltage to a level conversion circuit are described in the prior art documents as follows. Patent Publication 1 (Japanese Laid-Open Patent Publication No. H10-214495) discloses a nonvolatile semiconductor storage device having a voltage switch circuit for switching a power supply voltage applied to a drive circuit according to a command of delete, write or the like. Patent Publication 2 (Japanese Laid-Open Patent Publication No. 2001-243786) discloses applying a high voltage as a power supply voltage according to a command signal. When such high voltage is applied, a ramp-up period and a ramp-down period are set. Patent Publication 3 (Japanese Laid-Open Patent Publication No. 2002-367388) discloses applying a high voltage stepwise by the use of a delayed command when the high voltage is applied according to a command signal.
However, all these patent publications relate to a voltage switch circuit which switches a power supply voltage applied to a drive circuit according to a command of delete, write, or the like. In other words, none of Patent Publications 1 to 3 discloses switching the power supply voltage according to the selected or non-selected state of the decoder circuit.
As described above, in a semiconductor device having a plurality of level conversion circuits, the most of the level conversion circuits are in the stand-by state to output a low level, but nevertheless a boost voltage is applied also to these level conversion circuits in the stand-by state. Moreover, a ripple is more prone to occur in the boost voltage applied to these level conversion circuits. A ripple in the boost voltage may cause leakage of current or occurrence of short-circuit in the gate oxide films of transistors forming the level conversion circuits.
It is therefore an object of the present invention to provide a voltage control circuit which is capable of preventing the deterioration or breakdown of transistors due to a ripple in the boost voltage by controlling the power supply voltage applied to level conversion circuits according to an output from decoder circuits, and to provide a semiconductor device having such voltage control circuit.